This application is based upon prior filed copending provisional application Ser. No. 60/115,532 filed Jan. 12, 1999.
The present invention relates to the field of semiconductor devices, and, more particularly, to a capacitor.
Capacitors are used extensively in electronic devices for storing an electric charge. A capacitor includes two conductive plates or electrodes separated by an insulator. The capacitance, or amount of charge held by the capacitor per applied voltage, depends upon the area of the plates, the distance between them, and the dielectric value of the insulator. Capacitors may be formed within a semiconductor device, such as, for example, a dynamic random access memory (DRAM) or an embedded DRAM.
As semiconductor memory devices become more highly integrated, the area occupied by the capacitor of a DRAM storage cell is reduced, thus decreasing the capacitance of the capacitor due to a smaller electrode surface area. However, a relatively large capacitance is desired to prevent loss of stored information. Therefore, it is desirable to reduce the cell dimensions and yet obtain a high capacitance, which achieves both high cell integration and reliable operation.
Instead of forming the capacitor on the substrate surface, capacitors are also formed above the substrate, i.e., they are stacked above the substrate. The surface area of the substrate can then be used for forming transistors. For example, U.S. Pat. No. 5,903,493 to Lee discloses a capacitor formed above a tungsten plug. The tungsten plug interfaces with an interconnection line, thus allowing different layers formed above the substrate to be connected. Such plugs may be anchored or tapered to secure the plug in the dielectric layer.
Current 0.25 and 0.2 micron semiconductor technology uses metal-oxide-metal (MOM) capacitors that are formed above tungsten plugs. However, these plugs can have surface defects such as seams, recesses, bulges or other topographical features which may cause MOM capacitor reliability and yield problems. For example, when the dielectric adjacent the tungsten plug is polished during a chemical mechanical polishing (CMP) step, the resulting tungsten plug may protrude or bulge upwardly above the dielectric layer.
In view of the foregoing background, it is therefore an object of the present invention to provide an integrated circuit capacitor with metal electrodes and with increased reliability of the capacitor.
This and other advantages, features and objects in accordance with the present invention are provided by an integrated circuit capacitor including a metal plug in a dielectric layer adjacent a substrate, with the metal plug having at least one topographical defect in an uppermost surface portion thereof. A lower metal electrode overlies the dielectric layer and the metal plug. The lower metal electrode preferably comprises, in stacked relation, a metal layer, a lower metal nitride layer, an aluminum layer, and an upper metal nitride layer. A capacitor dielectric layer overlies the lower metal electrode, and an upper metal electrode overlies the capacitor dielectric layer. An advantage of this structure is that the stack of metal layers of the lower metal electrode, will prevent undesired defects at the surface of the metal plug from adversely effecting device reliability or manufacturing yield. The aluminum and metal nitride layers may also desirably provide an etch stop layer to facilitate manufacturing.
The metal plug preferably comprises tungsten, and the at least one topographical defect may include at least one of a recess, a seam and a bulge. The metal layer of the lower metal electrode preferably comprises a refractory metal such as titanium. Each of the lower and upper metal nitride layers of the lower metal electrode preferably comprises a refractory metal nitride, such as titanium nitride. Also, the upper metal electrode may comprise, in stacked relation, a lower metal nitride layer, an aluminum layer, and an upper metal nitride layer. Each of the lower and upper metal nitride layers of the upper metal electrode may also comprise titanium nitride.
The advantages, features and objects in accordance with the present invention are also provided by a method of making an integrated circuit capacitor including the steps of forming a dielectric layer adjacent a substrate and forming a metal plug in the dielectric layer. The forming of the metal plug creates at least one undesirable topographical defect in an uppermost surface portion of the metal plug. The method further includes the step of forming a lower metal electrode overlying the dielectric layer and the metal plug. The lower metal electrode may comprise, in stacked relation, a metal layer, a lower metal nitride layer, an aluminum layer, and an upper metal nitride layer. A capacitor dielectric layer is formed over the lower metal electrode, and an upper metal electrode is formed over the capacitor dielectric layer.